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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 5 1 publication order number: ncp1608/d ncp1608 critical conduction mode pfc controller utilizing a transconductance error amplifier the ncp1608 is an active power factor correction (pfc) controller specifically designed for use as a pre?converter in ac?dc adapters, electronic ballasts, and other medium power off?line converters (typically up to 350 w). it uses critical conduction mode (crm) to ensure near unity power factor across a wide range of input voltages and output power. the ncp1608 minimizes the number of external components by integrating safety features, making it an excellent choice for designing robust pfc stages. it is available in a soic?8 package. general features ? near unity power factor ? no input voltage sensing requirement ? latching pwm for cycle?by?cycle on time control (voltage mode) ? wide control range for high power application (>150 w) noise immunity ? transconductance error amplifier ? high precision voltage reference ( 1.6% over the temperature range) ? very low startup current consumption ( 35 a) ? low typical operating current consumption (2.1 ma) ? source 500 ma/sink 800 ma totem pole gate driver ? undervoltage lockout with hysteresis ? pin?to?pin compatible with industry standards ? this is a pb?free and halide?free device safety features ? overvoltage protection ? undervoltage protection ? open/floating feedback loop protection ? overcurrent protection ? accurate and programmable on time limitation typical applications ? solid state lighting ? electronic light ballast ? ac adapters, tvs, monitors ? all off?line appliances requiring power factor correction soic?8 d suffix case 751 marking diagram pin connection 1 8 a = assembly location l = wafer lot y = year w = work week = pb?free package 1608b alyw 1 8 fb control ct cs v cc drv gnd zcd (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification s brochure, brd801 1/d. ncp1608bdr2g soic?8 (pb?free) 2500 / tape & ree l www. onsemi.com
ncp1608 www. onsemi.com 2 figure 1. typical application + ac line emi filter 1 4 3 2 8 5 6 7 + c bulk load (ballast, smps, etc.) ncp1608 v out r sense c in r zcd r out1 r out2 c comp v cc c t d l fb control ct cs gnd zcd drv v cc v in n b :n zcd m figure 2. block diagram e/a demag uvp fault ocp leb off timer reset pwm r q s (enable ea) haversine drv r sense q all sr latches are reset dominant zcd clamp ovp uvlo uvlo v cc drv gnd pok v dd v cc v dd pok v dd v cc v ddgd v dd reg + + - v out c bulk r out1 r out2 d fb control zcd r zcd c t c t cs c comp l + + ? + v ovp pok ? + v uvp r fb v ref + g m ? + v control v dd v ddgd r q s q r q s q r q s q r q s q v zcd(trig) ? + + v zcd(arm) + v ilim + ? + ? + v dd add ct offset i charge v eah clamp ? + n b :n zcd v in m
ncp1608 www. onsemi.com 3 table 1. pin function description pin name function 1 fb the fb pin is the inverting input of the internal error amplifier. a resistor divider scales the output voltage to v ref to maintain regulation. the feedback voltage is used for overvoltage and undervoltage protections. the controller is disabled when this pin is forced to a voltage less than v uvp , a voltage greater than v ovp , or floating. 2 control the control pin is the output of the internal error amplifier. a compensation network is connected between the control pin and ground to set the loop bandwidth. a low bandwidth yields a high power factor and a low total harmonic distortion (thd). 3 ct the ct pin sources a current to charge an external timing capacitor. the circuit controls the power switch on time by comparing the ct voltage to an internal voltage derived from v control . the ct pin discharges the external timing capacitor at the end of the on time. 4 cs the cs pin limits the cycle?by?cycle current through the power switch. when the cs voltage exceeds v ilim , the drive turns off. the sense resistor that connects to the cs pin programs the maximum switch current. 5 zcd the voltage of an auxiliary winding is sensed by this pin to detect the inductor demagnetization for crm operation. 6 gnd the gnd pin is analog ground. 7 drv the integrated driver has a typical source impedance of 12 and a typical sink impedance of 6 . 8 v cc the v cc pin is the positive supply of the controller. the controller is enabled when v cc exceeds v cc(on) and is disabled when v cc decreases to less than v cc(off) . table 2. maximum ratings rating symbol value unit fb voltage v fb ?0.3 to 10 v fb current i fb 10 ma control v oltage v control ?0.3 to 6.5 v control current i control ?2 to 10 ma ct voltage v ct ?0.3 to 6 v ct current i ct 10 ma cs voltage v cs ?0.3 to 6 v cs current i cs 10 ma zcd voltage v zcd ?0.3 to 10 v zcd current i zcd 10 ma drv voltage v drv ?0.3 to v cc v drv sink current i drv(sink) 800 ma drv source current i drv(source) 500 ma supply v oltage v cc ?0.3 to 20 v supply current i cc 20 ma power dissipation (t a = 70 c, 2.0 oz cu, 55 mm 2 printed circuit copper clad) p d 450 mw thermal resistance junction?to?ambient (2.0 oz cu, 55 mm 2 printed circuit copper clad) junction?to?air, low conductivity pcb (note 3) junction?to?air, high conductivity pcb (note 4) r ja r ja r ja 178 168 127 c/w operating junction temperature range (note 5) t j ?55 to +125 c maximum junction t emperature t j(max) 150 c storage temperature range t stg ?65 to +150 c lead temperature (soldering, 10 s) t l 300 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. this device series contains esd protection and exceeds the following tests: pins 1 ? 8: human body model 2000 v per jedec standard jesd22?a1 14e. pins 1? 8: charged device model 1000 v per jedec standard jesd22?c101e. 2. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 3. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection or zero air flow. 5. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1608 www. onsemi.com 4 table 3. electrical characteristics v fb = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ?55 c to 125 c (note 6), v cc = 12 v, unless otherwise specified) characteristic test conditions symbol min typ max unit startup and supply circuits startup voltage threshold v cc increasing v cc(on) 11 12 12.5 v minimum operating v oltage v cc decreasing v cc(off) 8.8 9.5 10.2 v supply voltage hysteresis h uvlo 2.2 2.5 2.8 v startup current consumption 0 v < v cc < v cc(on) ? 200 mv i cc(startup) ? 24 35 a no load switching current consumption c drv = open, 70 khz switching, v cs = 2 v i cc1 ? 1.4 1.7 ma switching current consumption 70 khz switching, v cs = 2 v i cc2 ? 2.1 2.6 ma fault condition current consumption no switching, v fb = 0 v i cc(fault) ? 0.75 0.95 ma overvoltage and undervoltage protection overvoltage detect threshold v fb = increasing v ovp /v ref 105 106 108 % overvoltage hysteresis v ovp(hys) 20 60 100 mv overvoltage detect threshold propagation delay v fb = 2 v to 3 v ramp, dv/dt = 1 v/ s v fb = v ovp to v drv = 10% t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) t ovp 300 210 500 500 800 800 ns undervoltage detect threshold v fb = decreasing v uvp 0.25 0.31 0.4 v undervoltage detect threshold propa- gation delay v fb = 1 v to 0 v ramp, dv/dt = 10 v/ s v fb = v uvp to v drv = 10% t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) t uvp 100 50 200 200 300 300 ns error amplifier voltage reference t j = 25 c t j = ?40 c to 125 c t j = ?55 c to 125 c (note 6) v ref 2.475 2.460 2.450 2.500 2.500 2.500 2.525 2.540 2.540 v voltage reference line regulation v cc(on) + 200 mv < v cc < 20 v v ref(line) ?10 ? 10 mv error amplifier current capability v fb = 2.6 v v fb = 1.08*v ref v fb = 0.5 v t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) i ea(sink) i ea(sink)ovp i ea(source) 6 10 ?250 ?250 10 20 ?210 ?210 20 30 ?110 ?88 a transconductance v fb = 2.4 v to 2.6 v t j = 25 c t j = ?40 c to 125 c t j = ?55 c to +125 c (note 6) gm 90 70 70 110 110 110 120 135 150 s feedback pin internal pull?down resistor v fb = v uvp to v ref r fb 2 4.6 10 m feedback bias current v fb = 2.5 v t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) i fb 0.25 0.2 0.54 0.54 1.25 1.25 a control bias current v fb = 0 v i control ?1 ? 1 a maximum control v oltage i control(pullup) = 10 a, v fb = v ref t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) v eah 5 5 5.5 5.5 6 6.05 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1608 www. onsemi.com 5 table 3. electrical characteristics (continued) v fb = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ?55 c to 125 c (note 6), v cc = 12 v, unless otherwise specified) characteristic unit max typ min symbol test conditions error amplifier minimum control voltage to generate drive pulses v control = decreasing until v drv is low, v ct = 0 v t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) ct (offset) 0.37 0.37 0.65 0.65 0.88 1.1 v control voltage range v eah ? ct (offset) v ea(diff) 4.5 4.9 5.3 v ramp control ct peak voltage v control = open v ct(max) 4.775 4.93 5.025 v on time capacitor charge current v control = open v ct = 0 v to v ct(max) i charge 235 275 297 a ct capacitor discharge duration v control = open v ct = v ct(max) ?100 mv to 500 mv t ct(discharge) ? 50 150 ns pwm propagation delay dv/dt = 30 v/ s v ct = v control ? ct (offset) to v drv = 10% t pwm ? 130 220 ns current sense current sense voltage threshold v ilim 0.45 0.5 0.55 v leading edge blanking duration v cs = 2 v, v drv = 90% to 10% t leb 100 190 350 ns overcurrent detection propagation de- lay dv/dt = 10 v/ s v cs = v ilim to v drv = 10% t cs 40 100 170 ns current sense bias current v cs = 2 v i cs ?1 ? 1 a zero current detection zcd arming threshold v zcd = increasing v zcd(arm) 1.25 1.4 1.55 v zcd triggering threshold v zcd = decreasing v zcd(trig) 0.6 0.7 0.83 v zcd hysteresis v zcd(hys) 500 700 900 mv zcd bias current v zcd = 5 v i zcd ?2 ? +2 a positive clamp voltage i zcd = 3 ma t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) v cl(pos) 9.8 9.2 10 10 12 12 v negative clamp v oltage i zcd = ?2 ma t j = ?40 c to +125 c t j = ?55 c to +125 c (note 6) v cl(neg) ?0.9 ?1.1 ?0.7 ?0.7 ?0.5 ?0.5 v zcd propagation delay v zcd = 2 v to 0 v ramp, dv/dt = 20 v/ s v zcd = v zcd(trig) to v drv = 90% t zcd ? 100 170 ns minimum zcd pulse width t sync ? 70 ? ns maximum off time in absence of zcd transition falling v drv = 10% to rising v drv = 90% t start 75 165 300 s drive drive resistance i source = 100 ma i sink = 100 ma r oh r ol ? ? 12 6 20 13 rise time 10% to 90% t rise ? 35 80 ns fall time 90% to 10% t fall ? 25 70 ns drive low voltage v cc = v cc(on) ?200 mv, i sink = 10 ma v out(start) ? ? 0.2 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. for coldest temperature, qa sampling at ?40 c in production and ?55 c specification is guaranteed by characterization.
ncp1608 www. onsemi.com 6 typical characteristics figure 3. overvoltage detect threshold vs. junction temperature figure 4. overvoltage hysteresis vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 100 75 50 25 0 ?25 ?50 105.0 105.5 106.0 106.5 107.0 150 100 75 25 0 ?25 ?50 40 50 60 70 80 v ovp /v ref , overvoltage detect threshold v ovp(hys) , overvoltage hyster- esis (mv) 125 figure 5. undervoltage detect threshold vs. junction temperature figure 6. feedback pin internal pull?down resistor vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.300 0.305 0.315 0.320 0.325 0.330 125 100 75 50 25 0 ?25 ?50 0 1 2 6 7 v uvp , undervoltage detect threshold (v) r fb , feedback pin internal pull? down resistor (m ) 0.310 150 150 figure 7. reference voltage vs. junction temperature figure 8. error amplifier output current vs. feedback voltage t j , junction temperature ( c) v fb , feedback voltage (v) 125 100 75 50 25 0 ?25 ?50 2.46 2.47 2.48 2.49 2.50 2.52 2.53 2.54 3.0 2.5 2.0 1.5 1.0 0.5 0 ?250 ?100 ?50 0 50 100 v ref , reference voltage (v) i ea , error amplifier output cur- rent ( a) 150 device in uvp 50 125 3 4 5 2.51 ?200 ?150
ncp1608 www. onsemi.com 7 typical characteristics figure 9. error amplifier sink current vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 6 8 10 12 14 16 i ea(sink) , error amplifier sink current ( a) 150 v fb = 2.6 v t j , junction temperature ( c) f, frequency (khz) 125 100 75 50 25 0 ?25 ?50 85 90 95 105 110 120 125 100 10 1 0.1 0.01 200 0 20 60 100 140 160 t j , junction temperature ( c) t j , junction temperature ( c) 150 125 100 75 25 0 ?25 ?50 0.3 0.4 0.5 0.7 0.8 1.0 125 100 75 50 25 0 ?25 ?50 264 266 270 274 278 gm, error amplifier transconductance ( s) gm, error amplifier transconductance ( s) ct (offset) , minimum control voltage to generate drive pulses (v) i charge , ct charge current ( a) 150 1000 50 150 figure 10. error amplifier source current vs. junction temperature 180 185 190 195 200 205 215 220 ?50 ?25 0 25 50 75 100 125 150 t j , junction temperature ( c) i ea(source) , error amplifier source current ( a) figure 11. error amplifier t ransconductance vs. junction temperature figure 12. error amplifier t ransconductance and phase vs. frequency figure 13. minimum control voltage to generate drive pulses vs. junction temperature figure 14. on time capacitor charge current vs. junction temperature v fb = 0.5 v 210 100 115 40 80 120 180 phase transconductance r control = 100 k c control = 2 pf v fb = 2.5 vdc, 1 vac v cc = 12 v t a = 25 c 200 0 20 60 100 140 160 40 80 120 180 , phase (degrees) 0.6 0.9 268 272 276
ncp1608 www. onsemi.com 8 typical characteristics figure 15. ct peak voltage vs. junction temperature figure 16. pwm propagation delay vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 100 75 50 25 0 ?25 ?50 4.0 4.5 5.0 5.5 6.0 100 110 120 130 140 150 160 170 figure 17. current sense voltage threshold vs. junction temperature figure 18. leading edge blanking duration vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.480 0.485 0.490 0.495 0.500 0.505 0.515 0.520 180 190 200 210 220 figure 19. maximum off time in absence of zcd transition vs. junction temperature figure 20. drive resistance vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 150 155 160 165 175 180 185 190 125 100 75 50 25 0 ?25 ?50 0 2 4 8 10 14 16 18 v ct(max) , ct peak voltage (v) t pwm , pwm propagation delay (ns) v ilim , current sense voltage threshold (v) t leb , leading edge blanking du- ration (ns) t start , maximum off time in ab- sence of zcd transition ( s) drive resistance ( ) 125 150 100 75 50 25 0 ?25 ?50 125 150 0.510 125 100 75 50 25 0 ?25 ?50 150 170 150 150 6 12 r oh r ol
ncp1608 www. onsemi.com 9 typical characteristics figure 21. supply voltage thresholds vs. junction temperature figure 22. startup current consumption vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 8 9 10 11 12 13 14 16 18 20 22 24 26 figure 23. switching current consumption vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 2.00 2.02 2.04 2.06 2.08 2.10 2.14 2.16 v cc , supply voltage thresh- olds (v) i cc(startup) , startup current consumption ( a) i cc2 , switching current con- sumption (ma) 150 v cc(on) v cc(off) 125 100 75 50 25 0 ?25 ?50 150 150 2.12
ncp1608 www. onsemi.com 10 introduction the ncp1608 is a voltage mode, power factor correction (pfc) controller designed to drive cost?effective pre-converters to comply with line current harmonic regulations. this controller operates in critical conduction mode (crm) suitable for applications up to 350 w. its voltage mode scheme enables it to obtain near unity power factor without the need for a line-sensing network. a high precision transconductance error amplifier regulates the output voltage. the controller implements comprehensive safety features for robust designs. the key features of the ncp1608 are: ? constant on time (voltage mode) crm operation. a high power factor is achieved without the need for input voltage sensing. this enables low standby power consumption. ? accurate and programmable on time limitation. the ncp1608 uses an accurate current source and an external capacitor to generate the on time. ? wide control range. in high power applications (> 150 w), inadvertent skipping can occur at high input voltage and high output power if noise immunity is not provided. the noise immunity provided by the ncp1608 prevents inadvertent skipping. ? high precision voltage reference. the error amplifier reference voltage is guaranteed at 2.5 v 1.6% over process and temperature. this results in accurate output voltages. ? low startup current consumption. the current consumption is reduced to a minimum (< 35 a) during startup, enabling fast, low loss charging of v cc . the ncp1608 includes undervoltage lockout and provides sufficient v cc hysteresis during startup to reduce the value of the v cc capacitor. ? powerful output driver. a source 500 ma/sink 800 ma totem pole gate driver enables rapid turn on and turn off times. this enables improved efficiencies and the ability to drive higher power mosfets. a combination of active and passive circuits ensures that the driver output voltage does not float high if v cc does not exceed v cc(on) . ? accurate fixed overvoltage protection (ovp). the ovp feature protects the pfc stage against excessive output overshoots that may damage the system. overshoots typically occur during startup or transient loads. ? undervoltage protection (uvp). the uvp feature protects the system if there is a disconnection in the power path to c bulk (i.e. c bulk is unable to charge). ? protection against open feedback loop. the ovp and uvp features protect against the disconnection of the output divider network to the fb pin. an internal resistor (r fb ) protects the system when the fb pin is floating (floating pin protection, fpp). ? overcurrent protection (ocp). the inductor peak current is accurately limited on a cycle-by-cycle basis. the maximum inductor peak current is adjustable by modifying the current sense resistor. an integrated leb filter reduces the probability of noise inadvertently triggering the overcurrent limit. ? shutdown feature. the pfc pre-converter is shutdown by forcing the fb pin voltage to less than v uvp . in shutdown mode, the i cc current consumption is reduced and the error amplifier is disabled. application information most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line (figure 24). this dc voltage is then processed by additional circuitry to drive the desired output. figure 24. t ypical circuit without pfc load converter rectifiers bulk storage capacitor + ac line this rectifying circuit consumes current from the line when the instantaneous ac voltage exceeds the capacitor voltage. this occurs near the line voltage peak and the resulting current is non-sinusoidal with a large harmonic content. this results in a reduced power factor (typically < 0.6). consequently, the apparent input power is higher than the real power delivered to the load. if multiple devices are connected to the same input line, the effect increases and a ?line sag? is produced (figure 25). figure 25. typical line waveforms without pfc line sag rectified dc ac line v oltage ac line current 0 0 v peak government regulations and utilities require reduced line current harmonic content. power factor correction is implemented with either a passive or an active circuit to comply with regulations. passive circuits contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. active circuits use a
ncp1608 www. onsemi.com 11 high frequency switching converter to regulate the input current harmonics. active circuits operate at a higher frequency, which enables them to be physically smaller, weigh less, and operate more efficiently than a passive circuit. with proper control of an active pfc stage, almost any complex load emulates a linear resistance, which significantly reduces the harmonic current content. active pfc circuits are the most popular way to meet harmonic content requirements because of the aforementioned benefits. generally, active pfc circuits consist of inserting a pfc pre?converter between the rectifier bridge and the bulk capacitor (figure 26). figure 26. active pfc pre?converter with the ncp1608 rectifiers + ac line high frequency bypass capacitor ncp1608 pfc pre?converter converter load + bulk storage capacitor the boost (or step up) converter is the most popular topology for active power factor correction. with the proper control, it produces a constant voltage while consuming a sinusoidal current from the line. for medium power (< 350 w) applications, crm is the preferred control method. crm occurs at the boundary between discontinuous conduction mode (dcm) and continuous conduction mode (ccm). in crm, the driver on time begins when the boost inductor current reaches zero. crm operation is an ideal choice for medium power pfc boost stages because it combines the reduced peak currents of ccm operation with the zero current switching of dcm operation. the operation and waveforms in a pfc boost converter are illustrated in figure 27. figure 27. schematic and waveforms of an ideal crm boost converter diode bridge ac line + ? l diode bridge ac line + ? l + the power switch is on the power switch is off critical conduction mode: next current cycle starts when the core is reset. inductor current + with the power switch voltage being about zero, the input voltage is applied across the inductor. the inductor current linearly increases with a (v in /l) slope. the inductor current flows through the diode. the inductor volt- age is (v out ? v in ) and the inductor current linearly decays with a (v out ? v in )/l slope. v out (v out ? v in )/l i l(peak) i l v in v drain v drain v in /l v out v in if next cycle does not start then v drain rings towards v in + i l v in v drain
ncp1608 www. onsemi.com 12 when the switch is closed, the inductor current increases linearly to the peak value. when the switch opens, the inductor current linearly decreases to zero. when the inductor current decreases to zero, the drain voltage of the switch (v drain ) is floating and begins to decrease. if the next switching cycle does not begin, then v drain rings towards v in . a derivation of equations found in and8123 leads to the result that high power factor in crm operation is achieved when the on time (t on ) of the switch is constant during an ac cycle and is calculated using equation 1. t on 2 p out l vac 2 (eq. 1) where p out is the output power, l is the inductor value, is the efficiency, and vac is the rms input voltage. a description of the switching over an ac line cycle is illustrated in figure 28. the on time is constant, but the off time varies and is dependent on the instantaneous line voltage. the constant on time causes the peak inductor current (i l(peak) ) to scale with the ac line voltage. the ncp1608 represents an ideal method to implement a constant on time crm control in a cost?ef fective and robust solution by incorporating an accurate regulation circuit, a low current consumption startup circuit, and advanced protection features. figure 28. inductor waveform during crm operation on off mosfet i in (t) i l (t) v in (t) v in(peak) i l(peak) i in(peak) error amplifier regulation the ncp1608 regulates the boost output voltage using an internal error amplifier (ea). the negative terminal of the ea is pinned out to fb, the positive terminal is connected to a 2.5 v 1.6% reference (v ref ), and the ea output is pinned out to control (figure 29). a feature of using a transconductance error amplifier is that the fb pin voltage is only determined by the resistor divider network connected to the output voltage, not the operation of the amplifier. this enables the fb pin to be used for sensing overvoltage or undervoltage conditions independently of the error amplifier. figure 29. error amplifier and on time regulation circuits fb control ea + pwm block gm uvp + ovp + ovp fault (enable ea) uvp fault c comp v control v ref v out r out1 r out2 r fb t on t on(max) + ? + ? + ? v ovp v uvp pok v control v eah ct (offset) t pwm slope ct i charge
ncp1608 www. onsemi.com 13 a resistor divider (r out1 and r out2 ) scales down the boost output voltage (v out ) and is connected to the fb pin. if the output voltage is less than the target output voltage, then v fb is less than v ref and the ea increases the control voltage (v control ). this increases the on time of the driver, which increases the power delivered to the output. the increase in delivered power causes v out to increase until the target output voltage is achieved. alternatively, if v out is greater than the target output voltage, then v control decreases to cause the on time to decrease until v out decreases to the tar get output voltage. this cause and ef fect regulates v out so that the scaled down v out that is applied to fb through r out1 and r out2 is equal to v ref . the presence of r fb (4.6 m typical value) for fpp is included in the divider network calculation. the output voltage is set using equation 2: v out v ref r out1 r out2 r fb r out2 r fb 1 (eq. 2) the divider network bias current is selected to optimize the tradeoff of noise immunity and power dissipation. r out1 is calculated using the bias current and output voltage using equation 3: r out1 v out i bias(out) (eq. 3) where i bias(out) is the output divider network bias current. r out2 is dependent on v out , r out1 , and r fb . r out2 is calculated using equation 4: r out2 r out1 r fb r fb v out v ref 1 r out1 (eq. 4) the pfc stage consumes a sinusoidal current from a sinusoidal line voltage. the converter provides the load with a power that matches the average demand only. the output capacitor (c bulk ) compensates for the difference between the delivered power and the power consumed by the load. when the power delivered to the load is less than the power consumed by the load, c bulk discharges. when the delivered power is greater than the power consumed by the load, c bulk charges to store the excess energy. the situation is depicted in figure 30. figure 30. output voltage ripple for a constant output power v out p out p in iac vac due to the charging/discharging of c bulk , v out contains a ripple at a frequency of either 100 hz (for a 50 hz line frequency in europe) or 120 hz (for a 60 hz line frequency in the usa). the v out ripple is attenuated by the regulation loop to ensure v control is constant during the ac line cycle for the proper shaping of the line current. to ensure v control is constant during the ac line cycle, the loop bandwidth is typically set below 20 hz. a type 1 compensation network consists of a capacitor (c comp ) connected between the control and ground pins (see figure 1). the capacitor value that sets the loop bandwidth is calculated using equation 5: c comp gm 2 f cross (eq. 5) where f cross is the crossover frequency and gm is the error amplifier transconductance. the crossover frequency is set below 20 hz. on time sequence the switching pattern consists of constant on times and variable off times for a given rms input voltage and output load. the ncp1608 controls the on time with the capacitor connected to the ct pin. a current source charges the ct capacitor to a voltage derived from the control pin voltage (v ct(off) ). v ct(off) is calculated using equation 6: v ct(off) v control ?ct (offset) 2 p out l i charge vac 2 ct (eq. 6 ) when v ct(off) is reached, the drive turns off (figure 31).
ncp1608 www. onsemi.com 14 figure 31. on time generation control ct + ? pwm + drv i charge t on v control ? ct (offset) t on v ct v ct(off) v dd drv v control ct (offset) v control varies with the rms input voltage and output load, which naturally satisfies equation 1. the on time is constant during the ac line cycle if the values of compensation components are sufficient to filter out the v out ripple. the maximum on time of the controller occurs when v control is at the maximum. the ct capacitor is sized to ensure that the required on time is reached at maximum output power and the minimum input voltage condition. the on time is calculated using equation 7: t on ct v ct(max) i charge (eq. 7) combining equation 7 with equation 1, results in equation 8: ct 2 p out l max i charge vac ll 2 v ct(max) (eq. 8) to calculate the minimum ct value: v ct(max) = 4.775 v (minimum value), i charge = 297 a (maximum value), vac ll is the minimum rms input voltage, and l max is the maximum inductor value. off time sequence in crm operation, the on time is constant during the ac line cycle and the off time varies with the instantaneous input voltage. when the inductor current reaches zero, the drain voltage (v drain in figure 27) resonates towards v in . measuring v drain is a way to determine when the inductor current reaches zero. to measure the high voltage v drain directly is generally not economical or practical. instead, a winding is added to the boost inductor. this winding, called the zero current detection (zcd) winding, provides a scaled representation of the inductor voltage that is sensed by the controller. figure 32 shows waveforms of ideal crm operation using a zcd winding. figure 32. ideal crm waveforms using a zcd winding drv 0 a 0 v 0 v 0 v 0 v diode conduction mosfet conduction t sw t on t diode t off v cl(neg) v zcd(trig) v zcd(arm) v cl(pos) v zcd(wind),on v zcd v zcd(wind),off v zcd(wind) v out v drain i l(peak) i l the voltage induced on the zcd winding during the switch on time (v zcd(wind),on ) is calculated using equation 9: v zcd(wind),on ?v in n b :n zcd (eq. 9) where v in is the instantaneous input voltage and n b :n zcd is the turns ratio of the boost winding to the zcd winding. the voltage induced on the zcd winding during the switch off time (v zcd(wind),off ) is calculated using equation 10: v zcd(wind),off v out v in n b :n zcd (eq. 10) when the inductor current reaches zero, the zcd pin voltage (v zcd ) follows the zcd winding voltage (v zcd(wind) ) and begins to decrease and ring towards zero volts. the ncp1608 detects the falling edge of v zcd and turns the driver on. to ensure that a zcd event is not inadvertently detected, the ncp1608 logic verifies that v zcd exceeds v zcd(arm) and then senses that v zcd decreases to less than v zcd(trig) (figure 33).
ncp1608 www. onsemi.com 15 figure 33. implementation of the zcd block zcd + ? + demag + ? + reset dominant latch r q s drive zcd clamp r zcd v in n zcd n b r sense v zcd(arm) v zcd(trig) q this sequence achieves crm operation. the maximum v zcd(arm) sets the maximum turns ratio and is calculated using equation 11: n b :n zcd v out 2
vac hl v zcd(arm) (eq. 11) where vac hl is the maximum rms input voltage and v zcd(arm) = 1.55 v (maximum value). the ncp1608 prevents excessive voltages on the zcd pin by clamping v zcd . when the zcd winding is negative, the zcd pin is internally clamped to v cl(neg) . similarly, when the zcd winding is positive, the zcd pin is internally clamped to v cl(pos) . a resistor (r zcd in figure 33) is necessary to limit the current into the zcd pin. the maximum zcd pin current (i zcd(max) ) is limited to less than 10 ma. r zcd is calculated using equation 12: r zcd 2
vac hl i zcd(max) (n b :n zcd ) (eq. 12) the value of r zcd and the parasitic capacitance of the zcd pin determine when the zcd winding signal is detected and the drive turn on begins. a large r zcd value creates a long delay before detecting the zcd event. in this case, the controller operates in dcm and the power factor is reduced. if the r zcd value is too small, the drive turns on when the drain voltage is high and ef ficiency is reduced. a popular strategy for selecting r zcd is to use the r zcd value that achieves minimum drain voltage turn on. this value is found experimentally. figure 34 shows the realistic waveforms for crm operation due to r zcd and the zcd pin capacitance. figure 34. realistic crm waveforms using a zcd winding with r zcd and the zcd pin capacitance drv 0 a 0 v 0 v 0 v 0 v diode conduction mosfet conduction t z r zcd delay minimum voltage turn on t on t off t sw t diode v cl(neg) v zcd(trig) v zcd(arm) v cl(pos) v zcd(wind),on v zcd v zcd(wind),off v zcd(wind) v out v drain i l(peak) i l i l(neg)
ncp1608 www. onsemi.com 16 during the delay caused by r zcd and the zcd pin capacitance, the equivalent drain capacitance (c eq(drain) ) discharges through the path shown in figure 35. figure 35. equivalent drain capacitance discharge path + ac line emi filter + d l i in c in i l c bulk v out c eq(drain) c eq(drain) is the combined parasitic capacitances of the mosfet, the diode, and the inductor. c in is charged by the energy discharged by c eq(drain) . the charging of c in reverse biases the bridge rectifier and causes the input current (i in ) to decrease to zero. the zero input current causes thd to increase. to reduce thd, the ratio (t z / t sw ) is minimized, where t z is the period from when i l = 0 a to when the drive turns on. the ratio (t z / t sw ) is inversely proportional to the square root of l. during startup, there is no energy in the zcd winding and no voltage signal to activate the zcd comparators. this means that the drive never turns on. to enable the pfc stage to start under these conditions, an internal watchdog timer (t start ) is integrated into the controller. this timer turns the drive on if the drive has been off for more than 165 s (typical value). this feature is deactivated during a fault mode (ovp or uvp), and reactivated when the fault is removed. wide control range the ct charging threshold (v ct(off) ) decreases as the output power is decreased from the maximum output power to the minimum output power in the application. in high power applications (> 150 w), v control is reduced to a low voltage at a large output power and ct (offset) remains constant. the result is that v ct(off) is reduced to a low voltage at a large output power. the low v control and v ct(off) voltages are susceptible to noise. the large output power combined with the low v control and v ct(off) increase the probability of noise interfering with the control signals and on time duration (figures 36 and 37). the noise induces voltage spikes on the control pin and ct pin that reduces the drive on time from the on time determined by the feedback loop (t on(loop) ). the reduced on time causes the energy stored in the inductor (l) to be reduced. the result is that v zcd does not exceed v zcd(arm) and the drive remains off until t start expires. this sequence results in pulse skipping and reduced power factor. figure 36. control pin noise induced on time reduction and pulse skipping drv remains off drv is not exceeded 0 v noise induced voltage spike t start t on t on(loop) v zcd(arm) low v control voltage low v ct(off) voltage v control ? ct (offset) v control ct (offset) v ct v ct(off) v zcd v zcd(arm) v zcd(trig) v cl(neg)
ncp1608 www. onsemi.com 17 figure 37. ct pin noise induced on time reduction and pulse skipping noise induced voltage spike drv remains off drv is not exceeded 0 v t on t start t on(loop) v cl(neg) v zcd(trig) v zcd v zcd(arm) v zcd(arm) v ct(off) v ct v control ct (offset) low v control voltage low v ct(off) voltage v control ? ct (offset) the wide control range of the ncp1608 increases v control and v ct(off) in comparison to devices with less control range. figure 38 compares v ct(off) of the ncp1608 to a device with a 3 v control range for an application with the following parameters: p out = 250 w l = 200 h = 92% va c ll = 85 vac va c hl = 265 vac figure 38 shows that v ct(off) of the ncp1608 is 50% larger than the 3 v control range device. the 50% increase enables the ncp1608 to prevent inadvertent skipping at high input voltages and high output power. p out , output power (w) v ct(off) , ct charging threshold (v) 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 25 75 125 175 225 275 figure 38. comparison of ct charging threshold vs. output power ncp1608 v in = 265 vac 3 v control range startup generally, a resistor connected between the rectified ac line and v cc charges the v cc capacitor to v cc(on) . the low startup current consumption (< 35 a) enables minimized standby power dissipation and reduced startup durations. when v cc exceeds v cc(on) , the internal references and logic of the ncp1608 are enabled. the controller includes an undervoltage lockout (uvlo) feature that ensures that the ncp1608 is enabled until v cc decreases to less than v cc(off) . this hysteresis ensures sufficient time for the auxiliary winding to supply v cc (figure 39). figure 39. typical v cc startup waveform v cc v cc(on) v cc(off) when the pfc pre-converter is loaded by a switch?mode power supply (smps), it is generally preferable for the smps controller to startup first. the smps then supplies the ncp1608 v cc . advanced controllers, such as the ncp1230 or ncp1381, control the enabling of the pfc stage (see figure 40) and achieve optimal system performance. this sequence eliminates the startup resistors and improves the standby power dissipation of the system.
ncp1608 www. onsemi.com 18 figure 40. ncp1608 supplied by a downstream smps controller (ncp1230) 1 7 6 5 2 3 4 ncp1608 + + + + 1 7 6 5 2 3 4 ncp1230 pfc(vcc) 88 + d c bulk v cc + ? soft start when v cc exceeds v cc(on) , t start begins counting. when t start expires, the error amplifier is enabled and begins charging the compensation network. the drive is enabled when v control exceeds ct (offset) . the charging of the compensation network slowly increases the drive on time from the minimum time (t pwm ) to the steady state on time. this creates a natural soft start mode that reduces the stress of the power components (figure 41). output driver the ncp1608 includes a powerful output driver capable of sourcing 500 ma and sinking 800 ma. this enables the controller to drive power mosfets efficiently for medium power ( 350 w) applications. additionally, the driver stage provides both passive and active pull?down circuits (figure 42). the pull?down circuits force the driver output to a voltage less than the turn?on threshold voltage of a power mosfet when v cc(on) is not reached. figure 41. startup timing diagram showing the natural soft start of the control pin fb control natural soft start v cc(on) v cc(off) v cc i switch v ref ct (offset) v out t start figure 42. output driver stage and pull?down circuits uvlo drv gnd + ? + drv in uvlo v cc v dd reg v dd v ddgd v dd
ncp1608 www. onsemi.com 19 overvoltage protection (ovp) the low bandwidth of the feedback network causes active pfc stages to react to changes in output load or input voltages slowly. consequently, there is a risk of overshoots during startup, load steps, and line steps. for reliable operation, it is critical that overvoltage protection (ovp) prevents the output voltage from exceeding the ratings of the pfc stage components. the ncp1608 detects excessive output voltages and disables the driver until v out decreases to a safe level, which ensures that v out is within the pfc stage component ratings. an internal comparator connected to the fb pin provides the ovp protection. the ovp detection voltage is calculated using equation 13: v out(ovp) v ovp v ref v ref r out1 r out2 r fb r out2 r fb 1 (eq. 13) where v ovp /v ref is the ovp detection threshold. the value of c bulk is sized to ensure that ovp is not inadvertently triggered by the 100 hz or 120 hz ripple of v out . the minimum value of c bulk is calculated using equation 14: c bulk p out 2 v ripple(peak?peak) f line v out (eq. 14) where v ripple(peak-peak) is the peak?to?peak output voltage ripple and f line is the ac line frequency. v ripple(peak-peak) is calculated using equation 15: v ripple(peak?peak) 2 v out(ovp) v out (eq. 15) the ovp logic includes hysteresis (v ovp(hys) ) to ensure that v out has sufficient time to discharge before the ncp1608 attempts to restart and to ensure noise immunity. the output voltage at which the ncp1608 attempts a restart (v out(ovpl) ) is calculated using equation 16: v out(ovpl) v ovp v ref v ref v ovp(hys) r out1 r out2 r fb r out2 r fb 1 (eq. 16) figure 43 depicts the operation of the ovp circuitry. figure 43. ovp operation ovp fault drv v out(ovpl) v out(ovp) v out undervoltage protection (uvp) when the input voltage is applied to the pfc stage, v out is forced to equate to the peak of the line voltage. the ncp1608 detects an undervoltage fault if v out is unusually low, such that v fb is less than v uvp . during an uvp fault, the drive and error amplifier are disabled. the uvp feature protects the system if there is a disconnection in the power path to c bulk (i.e. c bulk is unable to charge) or if r out1 is disconnected. the output voltage that causes an uvp fault is calculated using equation 17: v out(uvp) v uvp r out1 r out2 r fb r out2 r fb 1 (eq. 17) open feedback loop protection the ncp1608 features comprehensive protection against open feedback loop conditions by including ovp, uvp, and fpp. figure 44 illustrates three conditions in which the feedback loop is open. the corresponding number below describes each condition shown in figure 44. 1. uvp protection: the connection from r out1 to the fb pin is open. r out2 pulls down the fb pin to ground. the uvp comparator detects an uvp fault and the drive and error amplifier are disabled. 2. ovp protection: the connection from r out2 to the fb pin is open. r out1 pulls up the fb pin to v out . the esd diode clamps the fb voltage to 10 v and r out1 limits the current into the fb pin. the ovp comparator detects an ovp fault and the drive is disabled.
ncp1608 www. onsemi.com 20 3. fpp protection: the fb pin is floating. r fb pulls down the fb voltage below v uvp . the uvp comparator detects an uvp fault and the drive and error amplifier are disabled. uvp and ovp protect the system from low bulk voltages and rapid operating point changes respectively, while fpp protects the system against floating feedback pin conditions. if fpp is not implemented and a manufacturing error causes the fb pin to float, then v fb is dependent on the coupling within the system and the surrounding environment. the coupled v fb may be within the regulation limits (i.e. v uvp < v fb < v ref ) and cause the controller to deliver excessive power. the result is that v out increases until a component fails due to the voltage stress. figure 44. open feedback loop protection fb control e/a + ? + + uvp fault (enable ea) + ? + ? ovp + condition 1 condition 2 condition 3 v out c bulk r out1 r out2 c comp v eah clamp r fb v ref v uvp v ovp pok g m v control overcurrent protection (ocp) the dedicated cs pin of the ncp1608 senses the inductor peak current and limits the driver on time if the voltage of the cs pin exceeds v ilim . the maximum inductor peak current is programmed by adjusting r sense . the inductor peak current is calculated using equation 18: i l(peak) v ilim r sense (eq. 18) an internal leb filter (figure 45) reduces the probability of switching noise inadvertently triggering the overcurrent limit. this filter blanks out the cs signal for a duration of t leb . if additional filtering is necessary, a small rc filter is connected between r sense and the cs pin. figure 45. ocp circuitry with optional external rc filter cs + ? + ocp leb drv optional r sense v ilim shutdown mode the ncp1608 enables the user to set the controller in a standby mode of operation. to shutdown the controller, the fb pin is forced to less than v uvp . when using the fb pin for shutdown (figure 46), the designer must ensure that no significant leakage current exists in the shutdown circuitry. any leakage current affects the output voltage regulation. figure 46. shutting down the pfc stage 1 4 3 2 8 5 6 7 ncp1608 shutdown r out2 r out1 v out
ncp1608 www. onsemi.com 21 application information on semiconductor provides an electronic design tool, a demonstration board, and an application note to facilitate the design of the ncp1608 and reduce development cycle time. all the tools can be downloaded or ordered at www.onsemi.com . the electronic design tool allows the user to easily determine most of the system parameters of a boost pre?converter. the demonstration board is a boost pre?converter that delivers 100 w at 400 v. the circuit schematic is shown in fi gure 47. the pre?converter design is described in application note and8396/d. figure 47. application schematic c3 dboost cin d1 cvcc2 + cbulk + cvcc rdrv rs1 u1 ncp1608 5 zcd 3 ct 6 gnd 4 cs 8 vcc 7 drv 1 fb 2 control ro1b lboost j3 j1 l2 f1 c2 q1 daux rzcd bridge ntc rct rctup1 rctup2 ro1a j2 czcd l1 dvcc ccomp1 ct1 rout2a ct2 rout2b rcs ccs rstart1 r1 rstart2 rs2 rs3 ddrv c1 rcomp1 ccomp t
ncp1608 www. onsemi.com 22 boost design equations components are identified in figure 1 input rms current iac p out vac (the efficiency of only the pfc stage) is generally in the range of 90 ? 95%. vac is the rms ac line input voltage. inductor peak current i l(peak) 2
2 p out vac the maximum inductor peak current occurs at the minimum line input voltage and maximum output power. inductor v alue l vac 2 v out 2
vac 2
v out p out f sw(min) f sw(min) is the minimum desired switching frequency. the maximum l is calculated at both the minimum line input voltage and maximum line input voltage. on time t on 2 l p out vac 2 the maximum on time occurs at the minimum line input voltage and maximum output power. off time t off t on v out vac sin 2
1 the off time is a maximum at the peak of the ac line voltage and approaches zero at the ac line zero crossings. theta ( ) represents the angle of the ac line voltage. switching frequency f sw vac 2 2 l p out 1 vac | sin | 2
v out on time capacitor ct 2 p out l max i charge vac ll 2 v ct(max) where vac ll is the minimum line input voltage and l max is the maximum inductor value. i charge and v ct(max) are shown in the specification table. inductor turns to zcd turns ratio n b :n zcd v out 2
vac hl v zcd(arm) where vac hl is the maximum line input voltage. v zcd(arm) is shown in the specification table. resistor from zcd winding to the zcd pin r zcd 2
vac hl i zcd(max) (n b :n zcd ) where i zcd(max) is maximum rated current for the zcd pin (10 ma). output voltage and output divider v out v ref r out1 r out2 r fb r out2 r fb 1 r out1 v out i bias(out) r out2 r out1 r fb r fb v out v ref 1 r out1 where v ref is the internal reference voltage and r fb is the pull?down resistor used for fpp. v ref and r fb are shown in the specification table. i bias(out) is the bias current of the output voltage divider. output voltage ovp detection and recovery v out(ovp) v ovp v ref v ref r out1 r out2 r fb r out2 r fb 1 v out(ovpl) v ovp v ref v ref ?v ovp(hys) r out1 r out2 r fb r out2 r fb 1 v ovp /v ref and v ovp(hys) are shown in the specification table. output voltage ripple and output capacitor value c bulk p out 2 v ripple(peak?peak) f line v out v ripple(peak?peak) 2 v out(ovp) v out where f line is the ac line frequency and v ripple(peak?peak) is the peak-to-peak output voltage ripple. use f line = 47 hz for universal input worst case. output capacitor rms current i c(rms) 2
32 p out 2 9 vac v out 2 i load(rms) 2
where i load(rms) is the rms load current.
ncp1608 www. onsemi.com 23 boost design equations components are identified in figure 1 (continued) output voltage uvp detection v out(uvp) v uvp r out1 r out2 r fb r out2 r fb 1 v uvp is shown in the specification table. inductor rms current i l(rms) 2 p out 3
vac output diode rms current i d(rms) 4 3 2
2
p out vac v out
mosfet rms current i m(rms) 2 3
p out vac 1 2
8 vac 3 v out
current sense resistor r sense v ilim i l(peak) p r sense i m(rms) 2 r sense v ilim is shown in the specification table. type 1 compensation c comp gm 2 f cross where f cross is the crossover frequency and is typically less than 20 hz. gm is shown in the specification table.
ncp1608 www. onsemi.com 24 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1608/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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